Dynamic forward error correction

ABSTRACT

A forward error correction (FEC) method is provided including an FEC dynamic central station and a plurality of FEC dynamic remote stations that transmit bearer data and corresponding error correction data therebetween during a plurality of time frames. The error rate of the communication channel is measured and the amount of error correction data transmitted is accordingly and dynamically adjusted, so that the minimum amount of overhead required to effectively transmit the error correction data is used.

FIELD OF THE INVENTION

The present inventions pertain to the field of error correction incommunication systems, including more specifically, forward errorcorrection arrangements.

BACKGROUND OF THE INVENTION

Digital communications systems utilize communication channels over whichtraffic data is communicated. These channels are typically bandwidthlimited, having a finite channel capacity. The channel capacity togetherwith other properties of the channel, such as various forms of noise andinterference, will, with statistical certainty, cause, or otherwiseresult, in the injection of error conditions in the traffic datacommunicated over the channel. The effects of these error conditions maybe particularly evident in wireless communications systems, whichutilize generally unpredictable over-the-air communications channelsthrough which remote stations communicate with a central station.

A technique for eliminating, or at least reducing, the effects of theseerror conditions is called Forward Error Correction (FEC). In general,the employment of an FEC technique entails transmitting error detectiondata and error correction data along with the bearer data. The errordetection data and error correction data are typically derived from thebearer data itself by employing an error detection algorithm and errorcorrection algorithm known to the receiver as well as the transmitter,and in the case of a digital wireless communications systems, a remotestation and a central station in communication with one another.

FEC techniques have been employed in Time Division Multiple Access(TDMA) and Code Division Multiple Access (CDMA) wireless communicationssystems. For example, TDMA systems typically allow communication betweena plurality of remote stations and a central station using the samefrequency band and transmitting bearer data between remote stations andthe central station during discrete time periods (i.e., each remotestation transmits and receives bearer data broken up into bearer databursts during respective time slots of cyclically repeating timeframes).

In wireless communication, prior to transmission, the central station orremote station appends or encodes the bearer data with error detectiondata and error correction data according to a respective error detectionalgorithm and error correction algorithm. The reciprocal remote stationor central station receives each error correctable bearer data packet,automatically corrects any errors in each error correctable bearer datapacket (within the limits of the error correction algorithm) byprocessing the error correctable bearer data packet according to theerror correction algorithm, and detects any residual errors in eachcorrected bearer data packet by processing the corrected bearer datapacket according to the error detection algorithm.

The use of an FEC technique to eliminate or reduce the effects oftransmission errors, however, does not come without a cost to thecommunications system. The transmission bandwidth available to a usertransmitting in a particular time slot in known systems is reduced bythe overhead required to transmit the error correction data. Thetransmission of error correction data with each error correctable bearerdata packet can require 100% or more overhead in some instances. Thisincrease in overhead typically results in either a longer time slot or areduction in the bandwidth available for the traffic data (for a fixedtransmission bit rate). In addition, in known wireless communicationssystems, the Bit Error Rate (BER) of the traffic data communicatedbetween a central station and a remote station depends on dynamicallyvarying conditions, such as, the relative distance between the remotestation and the central station, interference, environmental conditions,traffic data transmission rate, etc.

As a result, the BER of bearer data transmitted between the centralstation and a remote station varies with each particular remote stationand with time with respect to each remote station making it difficult tosystematically select an FEC error correction algorithm that optimizesboth the transmission overhead and error protection capability. Toprovide high quality communication between the central station and anygiven remote station during any given time period, the error correctionalgorithm is generally selected based on the worst-case BER, and is thusoverly robust in most situations, resulting in undesirably high overheadand reduced overall data throughput for the system.

There thus is a need for a communications system that employs an FECarrangement that among other things, maximizes the amount of bearer datatransmitted between the central station and any given remote station atany given time, while still providing an acceptable error rate.

SUMMARY OF THE INVENTION

The present inventions comprise a novel method of dynamically varyingthe transmission of error correction data in communications systems.

In a preferred method of the present inventions, a first plurality oferror correctable bearer data packets is transmitted between a firstcommunications device and a second communications device during a firstmulti-frame (i.e., a plurality of time frames). An initial errorcorrection algorithm is selected from a plurality of error correctionalgorithms, which is then employed to generate error correction data.The error correction data is transmitted with the bearer data packetsby, such as, e.g., appending or encoding the error correction datathereto, creating the first plurality of error correctable bearer datapackets. The plurality of error correction algorithms can comprise anynumber of different error correction algorithms, which may include noerror correction algorithm. Upon receipt of the first plurality of errorcorrectable bearer data packets, errors that are injected into the firstplurality of error correctable bearer data packets during thetransmission thereof are corrected within the limits of the selectederror correction algorithm.

The error rate level of the communications channel between the firstcommunications terminal and the second communications terminal isdetermined during the first multi-frame. The error rate level of thecommunications channel may be determined by such techniques as, e.g.,measuring the number of defective corrected bearer data packets (i.e.,block error rate (BLER)) or measuring the number of bit errors in theuncorrected bearer data packets (i.e., bit error rate (BER)). Asubsequent error correction algorithm, which may be the same as theinitial error correction algorithm, is selected from the plurality oferror correction algorithms based in part upon the determined error ratelevel.

A second plurality of error correctable bearer data packets istransmitted between the first communications terminal and the secondcommunications terminal during a second multi-frame. The subsequentselected error correction algorithm is employed to generate errorcorrection data, which is transmitted with the second plurality of errorcorrectable bearer data packets. The second plurality of errorcorrectable bearer data packets are corrected within the limits of thesecond selected error correction algorithm. The error rate level of thecommunication channel between the first communications terminal and thesecond communications terminal is determined during the secondmulti-frame. A third error correction algorithm, which can be the sameas or different from the second selected error correction algorithm, isselected from the plurality of error correction algorithms based in partupon the determined error rate level.

The third selected error correction algorithm is employed to correct thethird plurality of error correctable bearer data packets transmittedbetween the first communications terminal and the second communicationsterminal during the third multi-frame. This error correction algorithmselection and error correctable bearer data packet correction process isrepeated during future multi-frames.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a representative block diagram of a wireless communicationsystem cell showing an FEC dynamic central station communicating with aplurality of FEC dynamic remote stations;

FIG. 2 depicts TDMA/FDD formatted downlink time frames and uplink timeframes divided into a plurality of time slots;

FIG. 3 depicts TDMA/TDD formatted downlink/uplink time frames dividedinto a plurality of time slots;

FIG. 4A is a representative block diagram of the FEC dynamic centralstation and one of the FEC dynamic remote stations;

FIG. 4B is a representative block diagram of an alternative embodimentof the FEC dynamic central station and one of the FEC dynamic remotestations;

FIG. 5A is a representative block diagram of an FEC dynamic remotestation processor;

FIG. 5B is a representative block diagram of an alternative embodimentof an FEC dynamic remote station processor;

FIG. 6 is a representative block diagram of an FEC dynamic centralstation processor;

FIG. 7 depicts TDMA formatted multi-frames divided into a plurality oftime frames;

FIG. 8 depicts the arrangement of FIGS. 8A and 8B;

FIGS. 8A and 8B are flow diagram illustrating a protocol for dynamicallyselecting an error correction algorithm;

FIG. 9 depicts the arrangement of FIGS. 9A and 9B; and

FIGS. 9A and 9B are flow diagram illustrating an alternative protocolfor dynamically selecting an error correction algorithm.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 depicts a TDMA wireless communication system 100 arranged tooperate in accordance with a preferred embodiment of the presentinventions. An FEC dynamic central station 104 is depicted ascommunicating with respective FEC dynamic remote stations 106 within acell 102. The cell 102 can be a macro-cell, micro-cell, wireless localloop, or any network in which multiple communication devices cancommunicate with one another. The FEC dynamic central station 104 can bea base station, base station controller, mobile switching center, or anycommunication device that can communicate with multiple remote stations.The FEC dynamic remote stations 106 can be any combination of remoteterminals (e.g., mobile handsets, wireless modems, wired communicationterminals (R54), or wireless local loop terminals).

The FEC dynamic central station 104 and respective FEC dynamic remotestations 106 communicate in a Time Division Multiple Access/FrequencyDivision Duplex (TDMA/FDD) format. That is, respective communicationsbetween the FEC dynamic central station 104 and each of the FEC dynamicremote stations 106 are time isolated, and the downlink communicationbetween the FEC dynamic central station 104 and a particular FEC dynamicremote station 106 is frequency isolated from the uplink communicationbetween the FEC dynamic central station 104 and that particular FECdynamic remote station 106. The FEC dynamic central station 104transmits data to the FEC dynamic remote stations 106 over a singledownlink frequency, such as, 1960 MHZ, and the FEC dynamic remotestations 106 transmit data to the FEC dynamic central station 104 over asingle uplink frequency, such as, 1880 MHZ.

As shown in FIG. 2, the downlink frequency is divided into cyclicallyrepeating downlink time frames 108(1), and the uplink frequency isdivided into cyclically repeating uplink time frames 108(2). The timeframes 108(1)/(2) are further divided into respective sets of time slots110(1)/(2). The uplink time frames 108(2) are synchronized with thedownlink time frames 108(1).

The FEC dynamic remote stations 106 are respectively assigned time slots110(1) in the downlink time frames 108(1) during which they receivedownlink error correctable bearer data packets from the FEC dynamiccentral station 104 (in this case, time slots D1, D3, D5, and D6 forrespective FEC dynamic remote stations 1-4). As such, the FEC dynamiccentral station 104 is assigned the same time slots 110(1) during whichit transmits downlink error correctable bearer data packets to therespective FEC dynamic remote stations 106. The FEC dynamic remotestations 106 are respectively assigned time slots 110(2) in the uplinktime frames 108(2) during which they transmit uplink error correctablebearer data packets to the FEC dynamic central station 104 (in thiscase, time slots U4, U6, U8, and U1 for respective FEC dynamic remotestations 1-4). As such, the FEC dynamic central station 104 is assignedthe same respective time slots 110 during which it receives uplink errorcorrectable bearer data packets from the respective FEC dynamic remotestations 106. As can be seen, several time slots of delay, and in thiscase three, are induced between corresponding downlink time slots 110(1)and uplink time slots 110(2) to obviate the need for installingadditional equipment in the FEC dynamic remote stations 106. Dependingon the particular protocol of the system, the empty time slots110(1)/(2) are used as idle time slots for anticipated usage by otherFEC dynamic remote stations 106, or alternatively, to support variousother functions, such as transmission of control data between the FECdynamic central station 104 and the FEC dynamic remote stations 106 ortransmission of broadcast data from the FEC dynamic central station 104.

Alternatively, the wireless communications system 100 is configured in aTDMA/TDD format, wherein a single frequency is utilized for bothdownlink and uplink transmission of bearer data, and the downlinkcommunication between the FEC dynamic central station 104 and aparticular FEC dynamic remote station 106 is time isolated from theuplink communication between the FEC dynamic central station 104 andthat particular FEC dynamic remote station 106. As shown in FIG. 3, thedownlink/uplink frequency is divided into cyclically repeating timeframes 108(3), which are further divided into time slots 110(3). Half ofthe time slots 110(3) are dedicated to downlink transmissions of data,and half of the time slots 110(3) are dedicated to uplink transmissionsof data. It should be noted, however, that number of time slots 110(3)dedicated to the respective downlink and uplink transmissions can beunbalanced. Each FEC dynamic remote station 106 is assigned a pair oftime slots 110(3) during which it can respectively receive downlinkerror correctable bearer data packets from the FEC dynamic centralstation 104 and transmit uplink error correctable bearer data packets tothe FEC dynamic central station 104 (in this case, time slots (D1,U1),(D2,U2), (D3,U3), and (D4,U4) for respective FEC dynamic remote stations1-4). As such, the FEC dynamic central station 104 transmits downlinkerror correctable bearer data packets to the respective FEC dynamicremote stations 106 and receives uplink error correctable bearer datapackets from the respective FEC dynamic remote stations 106 during thesame pairs of time slots 110(3).

Although FIG. 1 depicts only four FEC dynamic remote stations 106 incommunication with the FEC dynamic central station 104 over a singlefrequency pair (TDMA/FDD) or single frequency (TDMA/TDD), in reality,the FEC dynamic central station 104 simultaneously communicates withmany other FEC dynamic remote stations 106 over a broad range offrequencies or frequency pairs.

FIG. 4A depicts a block diagram of the FEC dynamic central station 104and one of the FEC dynamic remote stations 106 of the wirelesscommunications system 100 in communication with each other. The FECdynamic central station 104 and the FEC dynamic remote station 106utilize a reciprocal adaptive FEC arrangement to ensure proper andefficient communication between the FEC dynamic central station 104 andthe FEC dynamic remote station 106.

The FEC dynamic remote station 106 transmits uplink error correctablebearer data packets to the FEC dynamic central station 104 in accordancewith the TDMA/FDD or TDMA/TDD arrangement as respectively depicted inFIGS. 2 and 3. The FEC dynamic remote station 106 comprises a processor112 that orchestrates the timing of the error correctable uplink bearerdata transmissions. The uplink error correctable bearer data packetscomprise uplink traffic data originating from an input/output device 114electrically coupled to the FEC dynamic remote station 106. Theinput/output device 114 is typically a voice encoder/decoder or datasource/sink, such as, e.g., a personal computer (PC). The processor 112is electrically coupled to and performs handshaking operations with theinput/output device 114 during which uplink traffic data is transferredfrom the input/output device 114. The amount of uplink traffic datatransferred from the input/output device 114 to form a single uplinkbearer data packet can be varied by the processor 112. The input/outputdevice 114 is electrically coupled and transfers uplink bearer datapackets to an error detection encoder 116.

The processor 112 is also electrically coupled and transfers uplinkcontrol data (such as, e.g., status data informing the FEC dynamiccentral station 104), to the error detection encoder 116. The errordetection encoder 116 appends the uplink bearer data packet with theuplink control data. The error detection encoder 116 also generateserror detection data according to a cyclical redundancy check (CRC)algorithm and appends the uplink bearer data packet with the errordetection data. The error detection encoder 116 can, however, employother types of error detection algorithms without straying from theprinciples taught by this invention.

The error detection encoder 116 is electrically coupled to an errorcorrection encoder 118, which appends error correction data onto theuplink bearer data packet according to an error correction algorithm,and in this case a Hamming error correction algorithm, to form an uplinkerror correctable bearer data packet. In alternative embodiments, asingle error correction/error detection encoder comprises the errorcorrection encoder 118 and error detection encoder 116.

The error correction encoder 118 is dynamic in that it is configured toemploy, on-command, no error correction algorithm, thus generating noerror correction data; a low-level Hamming error correction algorithm,which generates error correction data requiring 20% overhead to transmitfor each uplink error correctable bearer data packet; or a high-levelHamming error correction algorithm, which generates error correctiondata requiring 100% overhead to transmit for each uplink errorcorrectable bearer data packet. The overhead percentage is defined asthe amount of error correction data relative to the amount of trafficdata in an error correctable bearer data packet. As described furtherbelow, the processor 112 dynamically selects the particular errorcorrection algorithm to be employed by the error correction encoder 118.In alternative embodiments, the particular type and amount of errorcorrection algorithms available to the error correction encoder 118 varyfrom those described above. For instance, eleven error correctionalgorithms, whether of the Hamming type or otherwise, can be employed,with the overhead of the error correction algorithms varying by 10%between a range of 0% and 100%. In further alternative embodiments, anerror correction algorithm can be variable, so that, rather thanselecting an error correction algorithm, the overhead of the errorcorrection algorithm is varied.

The error correction encoder 118 is electrically coupled to a modulator120, which modulates the uplink error correctable bearer data packetonto a carrier frequency. The modulator 120 is electrically coupled totransmitter 122, which amplifies and filters the uplink errorcorrectable bearer data packet. The transmitter is electrically coupledto an antenna 124, which transmits the uplink error correctable bearerdata packet over-the-air to the FEC dynamic central station 104.

The FEC dynamic remote station 106 also receives downlink errorcorrectable bearer data packets from the FEC dynamic central station 104in accordance with the TDMA/FDD or TDMA/TDD arrangement respectivelydepicted in FIGS. 2 and 3. As with the uplink bearer data transmissions,the FEC dynamic remote station processor 112 orchestrates the timing ofthe downlink bearer data reception. The downlink error correctablebearer data packets comprise downlink traffic data originating from aninput/output device 114′ electrically coupled to the FEC dynamic centralstation 104. The input/output device 114′ on the FEC dynamic centralstation 104 side of the wireless communications system 100 is typicallyan interface to a communications network, such as, e.g., a PublicSwitched Telephone Network (PSTN), or a data network, such as, e.g., theinternet.

The antenna 124 receives a downlink error correctable bearer data packetover-the-air from the FEC dynamic central station 104. The antenna 124is electrically coupled to the receiver 126, which selects the downlinkerror correctable bearer data packet channel. The receiver 126 iselectrically coupled to a demodulator 128, which extracts the downlinkerror correctable bearer data packet from the radio frequency carrier.

The demodulator 128 is electrically coupled to an error correctiondecoder 130, which processes and corrects the downlink error correctablebearer data packet according to an error correction algorithm, and inthis case, a Hamming error correction algorithm. Like the errorcorrection encoder 118, the error correction decoder 130 is dynamic inthat it is configured to operate in a manner consistent with the encoderalgorithm applied to the current error correctable bearer data packet.As described further below, the processor 112 dynamically selects theparticular error correction algorithm to be employed by the errorcorrection decoder 130. In alternative embodiments, the particular typeand amount of error correction algorithms available to the errorcorrection decoder 130 vary from those described above.

The error correction decoder 130 can only correct the downlink errorcorrectable bearer data packet within the limits of the particular errorcorrection algorithm employed. Although the error correction decoder 130attempts to correct the downlink error correctable bearer data packet,it is possible that the error correction decoder 130 can output acorrected downlink error correctable bearer data packet with a residualerror.

The error correction decoder 130 is electrically coupled and transfersthe corrected downlink error correctable bearer data packet to an errordetection decoder 132, which processes and detects any residual errorsin the corrected downlink error correctable bearer data packetsaccording to an error detection algorithm, such as a CRC error detectionalgorithm. The error detection decoder 132 can, however, employ othertypes of error detection algorithms without straying from the principlestaught by this invention. In alternative embodiments, a single errorcorrection/error detection decoder comprises the error correctiondecoder 130 and error detection decoder 132.

The error detection decoder 132 separates the downlink control data fromthe corrected downlink bearer data packet, and may provide an indicationthat the corrected bearer data packet still has an error, initiating abearer data packet retransmission. The error detection decoder 132 iselectrically coupled and transfers the downlink bearer data packet tothe input/output device 114 as downlink traffic data. The errordetection decoder 132 is also electrically coupled and transfers thecontrol data to the processor 112. The processor 112 is electricallycoupled to and performs handshaking operations with the input/outputdevice 114 during which downlink traffic data is transferred to theinput/output device 114. The amount of downlink traffic data transferredto the input/output device 114 can be varied by the processor 112.

The FEC dynamic remote station processor 112 not only controls thetiming of the transmission and reception functions of the FEC dynamicremote station 106, but is also internally configured and arranged withthe input/output device 114, error correction encoder 118, errorcorrection decoder 130, and error detection decoder 132 to orchestratethe reciprocal dynamic FEC arrangement of the present invention.

As shown in FIG. 5A, the FEC dynamic remote station processor 112comprises a Central Processing Unit (CPU) 134, which performs theprocessing functions in the FEC dynamic remote station 106. Theprocessor 112 further comprises instructions that allow the FEC dynamicremote station 106 to dynamically generate uplink error correctablebearer data packets and dynamically correct downlink error correctablebearer data packets in accordance with the present inventions. Theseinstructions preferably take the form of a computer software programembedded in memory, such as, e.g., a ROM chip, or fixed logic, such as,e.g., an ASIC, which can be either on-board or separate from the CPU134. The FEC dynamic remote station processor 112 further comprisesvarious memory locations for the storage of status data concerning theFEC arrangement employed by the wireless communications system 100. Forthe purposes of illustration, these memory locations are depicted inFIG. 5A as registers. It should be understood, however, that any memorystorage vehicle that allows for the storage and access of data can beemployed.

The FEC dynamic remote station processor 112 tracks the respective errorcorrection algorithms that are employed by the error correction encoder118 and error correction decoder 130. The processor 112 comprises anuplink algorithm specification register 136, which stores a data value(A) indicating the type and level of the error correction algorithm thatis employed by the FEC dynamic remote station 106 to append the currentuplink error correctable bearer data packet with error correction data.The data value (A) stored in the uplink algorithm specification register136 is either equal to “0” indicating no error correction algorithm, “1”indicating the low-level error correction algorithm, or “2” indicatingthe high-level error correction algorithm. Again, the present inventionis not to be limited to these particular error correction algorithms andcan include other types of error correction algorithms without departingfrom the principles taught by this invention. As shown in FIG. 4A, theprocessor 112 is electrically coupled to the error correction encoder118, so that the processor 112 can, after accessing the uplink algorithmspecification register 136, transmit a control signal to the errorcorrection encoder 118, specifying the particular error correctionalgorithm to be employed by the error correction encoder 118 whenappending the current uplink error correctable bearer data packet witherror correction data.

The FEC dynamic remote station processor 112 comprises a downlinkalgorithm specification register 138, which stores a data value (B)indicating the type and level of the error correction algorithm employedby the FEC dynamic remote station 106 to correct the current downlinkerror correctable bearer data packet with error correction data. Thedata value (B) stored in the downlink algorithm specification register138 is equal to either “0” indicating no error correction algorithm, “1”indicating the low-level error correction algorithm, or “2” indicatingthe high-level error correction algorithm. As shown in FIG. 4A, theprocessor 112 is electrically coupled to the error correction decoder130, so that the processor 112 can, after the CPU 134 accesses thedownlink algorithm specification register 138, transmit a control signalto the error correction decoder 130 specifying the particular errorcorrection algorithm to be employed by the error correction decoder 130when correcting the current downlink error correctable bearer datapacket.

As shown in FIG. 7, cyclically repeating time frames 108 are groupedinto cyclically repeating multi-frames 156. The time frames 108 commonlyrepresent the TDMA/FDD formatted downlink time frames 108(1) and uplinktime frames 108(2) shown in FIG. 2 and the TDMA/TDD formatteddownlink/uplink time frames 108(3) shown in FIG. 3. The multi-frames 156commonly represent downlink multi-frames 156(1) and uplink time frames156(2) respectively comprising the TDMA/FDD formatted downlink timeframes 108(1) and uplink time frames 108(2), and the downlink/uplinkmulti-frames 156(3) comprising the TDMA/TDD formatted downlink/uplinktime frames 108(3). The number of time frames 108 in each multi-frame156 is dictated by the particular time frame 108 during which the FECdynamic remote station processor 112 selects an error correctionalgorithm. That is, the processor 112 only selects an error correctionalgorithm during a particular time frame 108 considered as the last timeframe 108 of the multi-frame 156, which may not have a fixed number oftime frames 108.

The processor 112 comprises a time frame incremental register 140, whichstores a data value (i) indicating the number of time frames 108 thathave passed in the current multi-frame 156. As shown in FIG. 4A, theerror detection decoder 132 is electrically coupled to the processor112, so that the error detection decoder 132 can send a control signalto the processor 112 indicating receipt of a downlink error correctablebearer data packet. For each control signal sent from the errordetection decoder 132 indicating that a downlink error correctablebearer data packet has been received by the FEC dynamic remote station106, the data value (i) in the time frame incremental register 140 isincremented by one. The processor 112 comprises a multi-frame register142, which stores a data value (L) indicating the time frame 108 of thecurrent multi-frame 156 during which the processor 112 selects the errorcorrection algorithm. The data value (L) is set by specifying the numberof time frames 108 in the current multi-frame 156.

The CPU 134 compares the data value (i) in the time frame incrementalregister 140 with the data value (L) in the multi-frame register 142 todetermine whether the current time frame 108 is the last time frame 108in the current multi-frame 156, and thus whether the error correctionalgorithm should be currently selected. For instance, if the data value(L) is set to 100, the current multi-frame 156 includes 100 time frames108. The CPU 134 selects the error correction algorithm if the datavalue (i) equals 100, indicating the 100th and last time frame 108 ofthe current set of 100 time frames 108.

The FEC dynamic remote station processor 112 determines an error ratelevel of the communication channel between the FEC dynamic remotestation 106 and the FEC dynamic central station 104, and moreparticularly an actual block error rate (BLER) level of the downlinkerror correctable bearer data packets transmitted during the currentmulti-frame 156. It should be noted that for purposes of thisspecification, the current BLER level refers to the current BLER or anyestimations thereof. The processor 112 comprises a BLER incrementalregister 144 that stores a data value (j) equal to the number ofcorrected downlink bearer data packets in which at least one residualerror, i.e., a defective corrected downlink bearer data packet, exists.The current BLER level can be determined from the data value (j). Theerror detection decoder 132 is electrically coupled to the processor112, so that the error detection decoder 132 can send to the processor112 a control signal indicating the presence of a defective correcteddownlink bearer data packet. For each control signal sent from the errordetection decoder 132 indicating the presence of a defective correcteddownlink bearer data packet, the data value (j) in BLER incrementalregister 144 is incremented by one.

As previously stated, during the last time frame 108 of the currentmulti-frame 156, the FEC dynamic remote station processor 112 selectsone of the three error correction algorithms to be employed by the errorcorrection encoder 118′ of the FEC dynamic central station 104 and theerror correction decoder 130 of the FEC dynamic remote station 106during the next multi-frame 156. The processor 112 comprises a minimumBLER threshold set register 146 and a maximum BLER threshold setregister 148, which respectively store data values (M) and (N)indicating the minimum tolerable BLER level, the triggering of whichwould indicate that the current error correction algorithm is toorobust, and the maximum tolerable BLER level, the triggering of whichwould indicate that the current error correction algorithm is not robustenough. Thus, data value (M) is set by specifying a minimum BLERthreshold level equal to a current BLER level that will triggerselection of the next lower error correction algorithm. Similarly, datavalue (N) is set by specifying a minimum BLER threshold level equal to acurrent BLER level that will trigger selection of the next higher errorcorrection algorithm. Because the data value (N) represents a higherthreshold than does the data value (M), the data value (N) is greaterthan the data value (M).

The CPU 134 respectively compares the data value (j) in the BLERincremental register 144 with the data value (M) in the minimum BLERthreshold set register 146 and the data value (N) in the maximum BLERthreshold set register 148 to determine which error correction algorithmis selected. For instance, if the data value (M) is set to 5, and thedata value (N) is set to 15, the CPU 134 selects the next lower errorcorrection algorithm if the data value (j) is less than 5. In this case,if the high-level error correction algorithm is currently being used,the CPU 134 selects the low-level error correction algorithm, and if thelow-level error correction algorithm or no error correction algorithm iscurrently being used, the CPU 134 selects no error correction algorithm.If the data value (j) is equal to or greater than 5 and equal to or lessthan 15, the CPU 134 selects the current error correction algorithm. Ifthe data value (j) is greater than 15, the CPU 134 selects the nexthigher error correction algorithm. In this case, if the low-level errorcorrection algorithm or the high-level error correction algorithm iscurrently being used, the CPU 134 selects the high-level errorcorrection algorithm, and if no error correction algorithm is currentlybeing used, the CPU 134 selects the low-level error correctionalgorithm.

In this manner, the CPU 134 maintains the number of defective correcteddownlink bearer data packets between a minimum and a maximum threshold,resulting in the employment of an error correction algorithm thatmaintains the current BLER level at a tolerable level while at the sametime not creating excessive overhead. It should be noted that theselection of the error correction algorithm is relative in that theerror correction algorithm selected is based on the error correctionalgorithm currently employed.

During dynamic communication conditions, wherein the quality of thecommunications channel may vary widely over time, the data value (L) inthe multi-frame register 142 is set to a relatively low value, so thatthe wireless communications system 100 can quickly compensate for thedynamic communication conditions. During stable communication conditionswhen the quality of the communications channel varies little over time,the data value (L) in the multi-frame register 142 is set to arelatively high value, so that the wireless communications system 100does not unnecessarily use CPU processing time.

The processor 112 determines the dynamic communication conditions andoccasionally adjusts the number of time frames 108 in a givenmulti-frame 156 by adjusting the data value (L) in the multi-frameregister 142. The processor 112 comprises a dynamic incremental register150, which stores a data value (k) indicating the number of consecutivetimes the CPU 134 has selected the same error correction algorithm. Ifthe CPU 134 selects the same error correction algorithm in the last timeframe 108 of the current multi-frame 156 as that selected by the CPU 134in the last time frame 108 of the previous multi-frame 156, the CPU 134increments the data value (k) in the dynamic incremental register byone.

The processor 112 comprises a low stability threshold set register 152and a high stability threshold set register 154, which respectivelystore a data value (P) indicating a low stability threshold, and a datavalue (Q) indicating a high stability threshold. The data value (P) isset by specifying a low stability threshold value equal to the number ofconsecutive selections of the same error correction algorithm on whichselection of either decreasing or maintaining the number of time frames108 in the next multi-frame 156 (i.e., data value (L)) is based. Thedata value (Q) is set by specifying a high stability threshold valueequal to the number of consecutive selections of the same errorcorrection algorithm on which selection of either maintaining orincreasing the number of time frames 108 in the next multi-frame 156 isbased. Because data value (Q) represents a higher threshold than doesthe data value (P), the data value (Q) is greater than the data value(P).

If a different error correction algorithm is selected, the CPU 134compares the data value (k) with the data value (P) in the low stabilitythreshold set register 152 to determine whether the data value (L) inthe multi-frame register 142 should be decreased or maintained. In thiscase, the data value (k) need not be compared to the data value (Q) inthe high stability threshold set register 154, since the necessity toincrease the data value (L) would only be triggered by a highly stablecommunication channel.

If the same error correction algorithm is selected, the CPU 134 comparesthe data value (k) with the data value (Q) in the high stabilitythreshold set register 152 to determine whether the data value (L) inthe multi-frame register 142 should be increased or maintained. In thiscase, the data value (k) need not be compared to the data value (P) inthe low stability threshold set register 154, since the necessity todecrease the data value (L) would only be triggered by a highly dynamiccommunication channel.

Thus, by way of non-limiting example, if the data value (P) is set to10, the data value (Q) is set to 30, the data value (L) is decreased ifthe data value (k) is less than 10 upon selection of a different errorcorrection algorithm, increased if the data value (k) is greater to orequal to 30 upon selection of the same error correction algorithm, andmaintained in all other cases.

Alternatively, rather than varying the data value (L) in the multi-frameregister 142 based on the number of consecutive times selection of thesame error correction algorithm occurs, as described above, variance ofthe data value (L) can be based on the ratio of the number of timesselection of an error correction algorithm was changed or not changedover a set number of multi-frames.

Referring to FIG. 4B, an alternative embodiment of an FEC dynamic remotestation 206 is described. In this embodiment, rather than determining acurrent BLER level based on the number of defective corrected downlinkbearer data packets received by the error detection decoder 132 aspreviously described, a current bit error rate (BER) level is determinedby measuring the number of bit errors in the downlink bearer datapackets received by the error correction decoder 130. It should be notedthat for purposes of this specification, the current BER level refers tothe actual BER or any estimations thereof. The FEC dynamic remotestation 206 is similar to the FEC dynamic remote station 106, with theexception that the error correction decoder 130 is electrically coupledto a processor 212 to transfer a control signal thereto indicating thenumber of bit errors that exist in an uncorrected downlink bearer datapacket. In such a case, the error detection encoder 116 and/or errordetection decoder 132 is not required for purposes of obtaining thecurrent BLER level, although in some cases, may be required for purposesof indicating to the FEC dynamic remote station 206 or base station 104(via an ARQ signal) that a defective corrected bearer data packet (i.e.,contains a residual error) has been received as described above.

As depicted in FIG. 5B, the processor 212 is similar to the processor112, with the exception that, instead of the BLER incremental register144, minimum BLER threshold set register 146 and maximum BLER thresholdset register 148, the processor 212 includes a BER incremental register244, first-level BER threshold set register 246 and a second-level BERthreshold set register 248. The BER incremental register 244 stores adata value (p) equal to the number of bit errors received by the FECdynamic remote station 204. The current BER level can be determined fromdata value (p). For each control signal sent from the error correctiondecoder 130 indicating the number of bit errors in an uncorrecteddownlink bearer data block, the data value (p) in the BER incrementalregister 244 is incremented by that number.

The first-level BER threshold set register 246 stores a data value (R)indicating the BER threshold level between selection of no errorcorrection algorithm and the low-level error correction algorithm. Thesecond-level BER threshold set register 248 stores a data value (S)indicating the BER threshold level between selection of the low-levelerror correction algorithm and the high-level error correctionalgorithm. Thus, data value (R) and data value (S) are set by definingthree ranges of bit error values that will respectively result in theselection of no error correction algorithm, the low-level errorcorrection algorithm, and the high-level error correction algorithm.

The CPU 234 respectively compares the data value (p) in the BERincremental register 244 with the data value (R) in the first-level BERthreshold set register 246 and the data value (S) in the second-levelBER threshold level to determine which error correction algorithm isselected. For instance, if the data value (R) is set to 20, and the datavalue (S) is set to 50, the CPU 234 selects no error correctionalgorithm if the data value (p) is less then 20, the low level errorcorrection algorithm if the data value (p) is equal to or greater than20 and less than 50, and the high-level error correction algorithm ifthe data value (p) is equal to or greater than 50.

It should be noted that the number of threshold levels will equal thenumber of error correction algorithms less one. Thus, if eleven errorcorrection algorithms can be selected, ten threshold levels will beneeded to define eleven ranges of detective bit values.

It should also be noted that by measuring the number of defective bitsreceived by the error correction decoder 130, the current BER level canbe more accurately obtained. That is, this alternative method takes intoaccount multiple bit errors in each downlink bearer data packet, as wellas bit errors that would otherwise not be detected because ofcorrection. Furthermore, because the current BER level is not based onthe detection of errors after correction, absolute selection of an errorcorrection algorithm can be accomplished. That is, selection of an errorcorrection algorithm is not based on the error correction algorithmcurrently employed, facilitating a more flexible error correctionalgorithm selection process. Thus, the high-level error correctionalgorithm can be selected even if the error correction algorithmcurrently used is no error correction algorithm, and vice versa.

The processor 112 comprises other registers, such as registers thatstore information concerning the time slots 110 during which the FECdynamic remote station 106 respectively transmits uplink errorcorrectable bearer data packets and receives downlink error correctablebearer data packets, as well as information relating to the FEC dynamicremote stations 106 in current communication with the FEC dynamiccentral station 104. For purposes of simplicity and ease ofillustration, however, discussion of these registers is omitted.

Preferably, the FEC dynamic remote station 106 includes any combinationof digitizing, source coding and decoding, interleaving andde-interleaving, burst formatting, or ciphering and de-cipheringfunctions. For the purposes of simplicity and ease of illustration,however, these functions are not illustrated and described.

Because the dynamic FEC arrangement employed by the wirelesscommunications system 100 is reciprocal, the componentry of the FECdynamic central station 104 is similar to that of the FEC dynamic remotestation 106. That is, as shown in FIG. 4A, the FEC dynamic centralstation 104, like the FEC dynamic remote station 106, comprises an errordetection encoder 116′, error correction encoder 118′, modulator 120′,transmitter 122′, and antenna 124′, which are all configured andarranged with each other and with the processor 112′ and input/outputdevice 114′ to facilitate the transmission of error correctable bearerdata packets to the FEC dynamic remote station 106. Likewise, the FECdynamic central station 104 further comprises a receiver 126′,demodulator 128′, error correction decoder 130′, and error detectiondecoder 132′, which are all configured and arranged with each other andwith the processor 112′, antenna 124′ and input/output device 114′ tofacilitate the reception of error correctable bearer data packetstransmitted by the FEC dynamic remote station 106.

As shown in FIG. 6, the FEC dynamic central station processor 112′, likethe FEC dynamic remote station processor 112, comprises a CPU 134′,which performs all of the processing functions in the FEC dynamiccentral station 104. The processor 112′ further comprises instructionsthat allow the FEC dynamic remote station 106 to dynamically generatedownlink error correctable bearer data packets and dynamically correctuplink error correctable bearer data packets. These instructions are inthe form of registers, and in particular a downlink algorithmspecification register 136′, which stores a data value (A′); uplinkalgorithm specification register 138′, which stores a data value (B′);time frame incremental register 140′, which stores a data value (i′);multi-frame register 142′, which stores a data value (L′); BLERincremental register 144′, which stores a data value (j′); minimum BLERthreshold set register 146′, which stores a data value (M′), maximumBLER threshold set register 148′, which stores a data value (N′);dynamic incremental register 150′, which stores a data value (k′); lowstability threshold set register 152′, which stores a data value (P);and high stability threshold set register 154′, which stores a datavalue (Q)

It should be noted that the processor 112′ provides for the measurementof current BLER levels. Quite similarly, but not shown, an FEC dynamiccentral station processor can be employed for providing the measurementof current BER levels, much like the FEC dynamic remote stationprocessor 212.

It should be further noted that, for purposes of simplicity indescribing the principles of this invention, only the componentry in theFEC dynamic central station 104 is necessary to communicate with variousFEC dynamic remote stations 106 over a single pair of downlink anduplink frequencies (TDMA/FDD) or a single downlink/uplink frequency pair(TDMA/TDD) is depicted in FIGS. 4A, 4B and 6. In reality, the FECdynamic central station 104 communicates with a multitude of FEC dynamicremote stations 106 over a range of downlink and uplink frequency pairsor downlink/uplink frequencies and includes other components notemployed in the FEC dynamic remote station 104, such as a multiplexerand demultiplexer. Furthermore, the FEC dynamic central stationprocessor 112′ includes a number of register sets equal to the systemcapacity of the wireless communications system 100, i.e., the number ofFEC dynamic remote stations 106 that the FEC dynamic central station 104is able to communicate with.

It should also be noted that the FEC arrangement employed by the FECdynamic central station 104 is independent from the FEC arrangementemployed by the FEC dynamic remote station 106, and thus, the errorcorrection algorithm selected by the FEC dynamic central station 104processor 112′ to append downlink error correctable bearer data packetswith error correction data does not necessarily correspond to the errorcorrection algorithm selected by the FEC dynamic remote stationprocessor 112 to append uplink error correctable bearer data packetswith error correction data. Also, the present inventions are not limitedto those wireless communications systems that employ a bilateral dynamicFEC arrangement as just described, but can also include wirelesscommunications systems that employ a unilateral or asymmetric dynamicFEC arrangement.

The following is a description of the operation of the wirelesscommunications system 100. During the initial handshaking operationbetween the FEC dynamic central station 104 and the FEC dynamic remotestation 106, data concerning the initial particulars of the FECarrangement of the wireless communications system 100, as well asinitiation data, such as identification data, time slot allocation data,and frequency allocation data is communicated between the FEC dynamiccentral station 104 and the FEC dynamic remote station 106.

If the wireless communications system 100 employs a TDMA/FDD format, thedownlink and uplink frequencies are different, and the FEC dynamicremote station 106 transmits and receives error correctable bearer datapackets during staggered time slots 110(1) and 110(2) of respectiveindependent time frames 108(1) and 108(2), as depicted in FIG. 2. If thewireless communications system 100 employs a TDMA/TDD format, thedownlink and uplink frequencies are the same, and the FEC dynamic remotestation 106 transmits and receives error correctable bearer data packetsduring different time slots 110(3) of the single time frame 108(3), asdepicted in FIG. 3. Frequency and time slot assignment is orchestratedby the FEC dynamic central station 104.

After the initial handshaking operations between the FEC dynamic centralstation 104 and the FEC dynamic remote station 106, the registers of theFEC dynamic central station processor 112′ and the FEC dynamic remotestation processor 112 are initialized, and downlink error correctablebearer data packets and uplink error correctable bearer data packets arealternately transmitted between the FEC dynamic central station 104 andthe FEC dynamic remote station 106.

With respect to the TDMA/FDD formatted system 100, the FEC dynamiccentral station 104 appends downlink error correctable bearer datapackets with error correction data according to a selected errorcorrection algorithm and respectively transmits these error correctablebearer data packets to the FEC dynamic remote station 106 in therespective downlink time frames 108(1) of a downlink multi-frame 156(1).The FEC dynamic remote station 106 corrects the error correctable bearerdata packets according to the selected error correction algorithm anddetermines a current BER level of the downlink communication channelbetween the FEC dynamic central station 104 and the FEC dynamic remotestation 106 during the last downlink time frame 108(1) of the downlinkmulti-frame 156(1) based on the bearer data received over the entiredownlink multi-frame 156(1). The FEC dynamic remote station 106 selects,based on the current BER level, an error correction algorithm to beemployed by the FEC dynamic central station 104 and the FEC dynamicremote station 106 to respectively append and correct the downlink errorcorrectable bearer data packets transmitted during the respectivedownlink time frames 108(1) of the next downlink multi-frame 156(1).

Likewise, the FEC dynamic remote station 106 appends uplink errorcorrectable bearer data packets with error correction data according toa selected error correction algorithm and respectively transmits theseerror correctable bearer data packets to the FEC dynamic central station104 in the respective uplink time frames 108(2) of an uplink multi-frame156(2). The FEC dynamic central station 104 corrects the errorcorrectable bearer data packets according to the selected errorcorrection algorithm and determines a current BER level of the uplinkcommunications channel between the FEC dynamic central station 104 andthe FEC dynamic remote station 106 during the last uplink time frame108(2) of the uplink multi-frame 156(2) based on the bearer datareceived over the entire uplink multi-frame 156(2). The FEC dynamiccentral station 104 selects, based on the current BER level, an errorcorrection algorithm to be employed by the FEC dynamic remote station106 and the FEC dynamic central station 104 to respectively append andcorrect the uplink error correctable bearer data packets transmittedduring the respective uplink time frames 108(2) of the next uplinkmulti-frame 156(2).

Referring to FIGS. 4-8, and more specifically to FIG. 8, the FEC dynamiccentral station processor 112′ and the FEC dynamic remote stationprocessor 112 perform various steps in effecting the downlinktransmission of consecutive error correctable bearer data packets duringthe respective downlink time frames 108(1) of each downlink multi-frame156(1) according to the dynamic FEC arrangement of the presentinvention.

At step 158, the data registers of the FEC dynamic central stationprocessor 112′ and FEC dynamic remote station processor 112 areinitialized. The data value (A′) in the downlink algorithm specificationregister 136′ of the FEC dynamic central station processor 112′ and thedata value (B) in the downlink algorithm specification register 138 ofthe FEC dynamic remote station processor 112 are initially both set to“0”, “1”, or “2” to specify the particular error correction algorithminitially and respectively employed by the FEC dynamic central station104 to generate error correction data and the FEC dynamic remote station106 to process and correct the first downlink error correctable bearerdata packet. The initial data values (A′) and (B) will depend on theparticular system requirements.

The data values (i), (j), and (k) in the respective time frameincremental register 140, BLER incremental register 144, and dynamicincremental register 150 of the FEC dynamic remote station processor 112are initialized to “0”. The data value (L) in the multi-frame register142 is initialized to set the number of time frames 108 in the firstmulti-frame 156. The data value (M) in the minimum BLER threshold setregister 146 and the data value (N) in the maximum BLER threshold setregister 148 are initialized to respectively set the minimum BLERthreshold level and the maximum BLER threshold level. The data value (P)in the low stability threshold set register 152 and the data value (Q)in the high stability threshold set register 154 are initialized torespectively set the low stability threshold and the high stabilitythreshold. The initial data values (L), (M), (N), (P), and (Q) will varywith the particulars of the wireless communications system 100 and areset accordingly.

At steps 160 to 176, the FEC dynamic central station processor 112′ andthe FEC dynamic remote station processor 112 respectively configure theerror correction encoder ′118 and the error detection decoder 132according to the current error correction algorithm, coordinate thetransmission, reception, and correction of respective downlink errorcorrectable bearer data packets during the current multi-frame 156, andselect an error correction algorithm to be employed during the nextmulti-frame 156.

At step 160, the FEC dynamic central station processor 112′ configuresthe error correction encoder 118′, so that it employs the particularerror correction algorithm specified in the downlink algorithmspecification register 136′ to generate the error correction data thatis to be appended to the current downlink error correctable bearer datapacket.The CPU 134′ accesses the downlink algorithm specificationregister 136′ to obtain the current data value (A′). If the data value(A′) equals “0”, the processor 112′ sends a control signal to the errorcorrection encoder 118′ indicating that no error correction algorithm beemployed. If the data value (A′) equals “1”, the processor 112′ sends acontrol signal to the error correction encoder 118′ indicating that thelow-level error correction algorithm be employed. If the data value (A′)equals any value but “0” or “1”, the processor 112′ sends a controlsignal to the error correction encoder 118′ indicating that thehigh-level error correction algorithm be employed.

At step 162, the FEC dynamic remote station processor 112 configures theerror correction decoder 130, so that it employs the particular errorcorrection algorithm specified in the downlink algorithm specificationregister 138 to process and correct the current downlink errorcorrectable bearer data packet. The CPU 134 accesses the downlinkalgorithm specification register 138 to obtain the current data value(B). If the data value (B) equals “0”, the processor 112 sends a controlsignal to the error correction decoder 130 indicating that no errorcorrection algorithm should be employed. If the data value (B) equals“1”, the processor 112 sends a control signal to the error correctiondecoder 130 indicating that the low-level error correction algorithmshould be employed. If the data value (B) equals any value but “0” or“1”, the processor 112 sends a control signal to the error correctiondecoder 130 indicating that the high-level error correction algorithmshould be employed. It should be noted that the data value (A′) in thedownlink algorithm specification register 136′ of the FEC dynamiccentral station processor 112′ is equal to the data value (B) in thedownlink algorithm specification register 138 of the FEC dynamic remotestation processor 112, since the error correction encoder 118′ of theFEC dynamic central station 104 and the error correction decoder 130 ofthe FEC dynamic remote station 106 employ the same error correctionalgorithm to respectively generate error correction data and correct thedownlink error correctable bearer data packet.

At step 164, the FEC dynamic central station processor 112′ directs theFEC dynamic central station 104 to transmit a downlink error correctablebearer data packet during a time slot 110(1) of the current downlinktime frame 108(1) which the FEC dynamic remote station 106 is designatedto receive an error correctable downlink bearer data packet (shown astime slot 3 in FIG. 7).

If an Automatic Retry Request (ARQ) signal transmitted by the FECdynamic remote station 106 indicating the receipt of a previouslytransmitted defective corrected bearer data packet, as described furtherbelow, was not received by the FEC dynamic central station 104, the FECdynamic central station processor 112′ directs the input/output device114′ electrically coupled to the FEC dynamic central station 104 totransfer downlink traffic data to the error detection encoder 116′ as adownlink bearer data packet. The amount of downlink traffic datatransferred to the error detection encoder 116′ will depend on theparticular error correction algorithm employed by the error correctionencoder 118′. That is, the processor 112′ directs the input/outputdevice 114′ to increase the amount of downlink traffic data transferredas error correction data overhead decreases. Contrariwise, the processor112′ directs the input/output device 114′ to decrease the amount ofdownlink traffic data transferred as the error correction data overheadincreases. The processor 112′ then transfers downlink control data tothe error detection encoder 116′ where it is appended to the downlinkbearer data packet. The error detection encoder 116′ generates errordetection data according to the CRC error detection algorithm andappends the downlink bearer data packet with the generated errordetection data. The error detection encoder 116′ then transfers thedownlink bearer data packet to the error correction encoder 118′. Theerror correction encoder 118′ then encodes the downlink bearer datapacket with error correction data according to the error correctionalgorithm specified by the processor 112′ to form an error correctabledownlink bearer data packet.

If an ARQ signal was received, the FEC dynamic central station processor112′ directs the input/output device 114′ to not transfer downlinktraffic data to the error correction encoder 118′. Instead, the previousdownlink error correctable bearer data packet stored in the errorcorrection encoder is re-transmitted as the current downlink errorcorrectable bearer data packet.

The downlink error correctable bearer data packet is then transferred tothe modulator 120′ and transmitter 112′, where it is respectivelymodulated with a downlink carrier frequency, and amplified and filtered.The downlink error correctable bearer data packet is then transferred tothe antenna 124′, where it is transmitted over-the-air to the antenna124 of the FEC dynamic remote station 106.

At step 166, the FEC dynamic remote station processor 112 directs theFEC dynamic remote station 106 to receive the downlink error correctablebearer data packet transmitted over-the-air from the FEC dynamic centralstation 104 during the downlink time slot 110(1) of the current downlinktime frame 108(1). The downlink error correctable bearer data packet isreceived by the antenna 124, and transferred to the receiver 126 and thedemodulator 128, where it is respectively filtered and demodulated fromthe carrier frequency. The downlink error correctable bearer data packetis then transferred to the error correction decoder 130. The errorcorrection decoder 130 then processes and corrects, within the limits ofthe error correction algorithm specified by the processor 112, thedownlink error correctable bearer data packet to generate a correcteddownlink bearer data packet. The corrected downlink bearer data packetis then transferred to the error detection decoder 132, where it isprocessed to determine the existence of any residual errors.

At step 168, the FEC dynamic remote station processor 112 remedies anyresidual errors in the corrected bearer data packet. If the errordetection decoder 132 does not sense a residual error in the correcteddownlink bearer data packet, the error detection decoder 132 sends acontrol signal to the processor 112 indicating that the error detectiondecoder 132 currently possesses a valid downlink bearer data packet. Thedownlink control data is then separated from the corrected downlinkbearer data packet. The valid downlink bearer data packet is transferredto the input/output device 114 electrically coupled to the FEC dynamicremote station 106 as downlink traffic data. The downlink control dataoriginating from the FEC dynamic central station 104 is transferred tothe processor 112, where it is accordingly processed. In response to noresidual errors in the corrected downlink bearer data packet, the CPU134 increments by one the data value (i) in the time frame incrementalregister 140.

If the error detection decoder 132 senses at least one residual error inthe corrected downlink bearer data packet, the error detection decoder132 sends a control signal to the processor 112 indicating that theerror detection decoder 132 currently possesses a defective correcteddownlink bearer data packet.

If the input/output device 114 is not delay-sensitive, such as, e.g., aPC, the defective corrected downlink bearer data packet is nottransferred to the input/output device 114. Instead, the FEC dynamicremote station processor 112 directs the FEC dynamic remote station 106to transmit an ARQ control signal during the next available control timeslot.

If the input/output device 114 is delay-sensitive, such as, e.g., avoice encoder/decoder, the downlink control data is separated from thecorrected downlink bearer data packet. The defective corrected downlinkbearer data packet is transferred to the input/output device 114electrically coupled to the FEC dynamic remote station 106 as downlinktraffic data. The processor 112, however, will send a control signal tothe input/output device 114 indicating the existence of defectivedownlink traffic data. The input/output device 114 then processes thedownlink traffic data accordingly. The downlink control data originatingfrom the FEC dynamic central station 104 is transferred to the processor112, where it is accordingly processed. In response to an indicateddefective corrected bearer data packet, the CPU 134 increments by one,both the data value (i) in the time frame incremental register 140 andthe data value (j) in the BLER incremental register 144.

At step 170, the FEC dynamic remote station processor 112 determineswhether the current downlink time frame 108(1) is the last time frame inthe current downlink multi-frame 156(1). That is, the FEC dynamic remotestation processor 112 determines whether the next error correctionalgorithm should currently be selected. The CPU 134 accesses the timeframe incremental register 140 to obtain the data value (i), and thus,the current downlink time frame 108(1). The CPU 134 also accesses themulti-frame register 144 to obtain the data value (L), and thus thenumber of downlink time frames 108(1) in the current multi-frame 156(1).The CPU 134 compares the data value (i) with the data value (L). If thedata value (i) does not equal the data value (L), the wirelesscommunications system 100 goes to step 164 whereat the FEC dynamiccentral station processor 112′ directs the FEC dynamic central station104 to transmit the next downlink error correctable bearer data packetduring the next downlink time frame 108(1) of the current downlinkmulti-frame 156(1).

If the data value (i) equals the data value (L), the FEC dynamic remotestation processor 106 selects, at step 172, the particular errorcorrection algorithm to be employed by the error correction encoder 118′of the FEC dynamic central station 104 and the error correction decoder130 of the FEC dynamic remote station 106 to respectively generate errorcorrection data and correct the error correctable bearer data packetstransmitted during the downlink time frames 108(1) of the next downlinkmulti-frame 156(1).

At step 172, if the current BLER level does not trigger the minimum BLERthreshold or the maximum BLER threshold, the current error correctionalgorithm employed is selected. If the current BLER level triggers theminimum BLER threshold, the next lower error correction algorithm isselected. If the current BLER level triggers the maximum BLER threshold,the next higher error correction algorithm is selected.

In this manner, the CPU 134 determines a current BLER level by accessingthe BLER incremental register 144 to obtain the current data value (j),and determines a minimum BLER threshold level by accessing the minimumBLER threshold set register 146 to obtain the current data value (M).The CPU 134 compares the data value (j) to the data value (M). If thedata value (j) is less than the data value (M), the CPU 134 accesses thedownlink algorithm specification register 138 to obtain the current datavalue (B), and thus the current error correction algorithm. If thecurrent data value (B) is less than or equal to “1”, the CPU 134 selectsthe data value (B) as “0”, indicating no error correction algorithmshould be selected. If the current value (B) is greater than “1”, theCPU 34 selects the data value (B) as 1, indicating that the low-levelerror correction algorithm should be selected.

If the data value (j) is greater than or equal to the data value (M),the CPU 134 determines the maximum BLER threshold by accessing themaximum BLER threshold set register 148 to obtain the current data value(N). The CPU 134 compares the data value (j) to the data value (N). Ifthe data value (j) is greater than the data value (N), the CPU 134accesses the downlink algorithm specification register 138 to obtain thecurrent data value (B), and thus the current error correction algorithm.If the current data value (B) equals “0”, the CPU 134 selects the datavalue (B) as “1”, indicating the low-level error correction algorithm.If the current data value (B) does not equal “0”, the CPU 134 selectsthe data value (B) as “2”, indicating the high-level error correctionalgorithm.

If the data value (j) is not greater than the data value (N), the CPU134 does not select a value for the data value (B), indicating that thecurrent error correction algorithm should be maintained. The CPU 134then increments the data value (k) in the dynamic incremental register150 indicating that a new error correction algorithm has not beenselected, i.e., the currently selected data value (B) is equal to thepreviously selected data value (B). As will be described in furtherdetail below, the data value (B) is not reset until approved by thecentral station 104.

Subsequent to proposed selection of the error correction algorithm, theCPU 134 resets the data value (i) in the time frame incremental register140 to “0” and the data value (j) in the BLER incremental register 144to “0”, so that they are initialized for the next multi-frame 156.

At step 174, the FEC dynamic remote station processor 112 determineswhether the data value (L) in the multi-frame register 142, and thus thenumber of downlink time frames 108(1) in the next downlink multi-frame156(1), should be changed with respect to the stability of thecommunication channel quality.

If the data value (k) in the dynamic incremental register 150 at step172 was not incremented indicating a change in the selection of theerror correction algorithm, the FEC dynamic remote station processor 212determines whether the number of downlink time frames 108(1) in the nextdownlink multi-frame 156(1) should be decreased or maintained. The CPU134 determines the number of consecutive times the same error correctionalgorithm has been selected by accessing the dynamic incrementalregister 150 to obtain the data value (k). The CPU 134 also determinesthe low stability threshold value by accessing the low stabilitythreshold set register 152 to obtain the data value (P). The CPU 134compares the data value (k) with the data value (P). If the data value(k) is less than the data value (P), the CPU 134 decrements the datavalue (L) in the multi-frame register 142 by a particular number,decreasing the number of time frames 108 in the next multi-frame 156. Ifthe data value (k) is not less than the data value (P), the CPU 134 doesnot change the data value (L) in the multi-frame register 142,maintaining the number of time frames 108 in the next multi-frame 156.Whether the data value (L) is decremented or maintained,. the CPU 134resets the data value (k) to “0”, so that the stability of thecommunication channel quality can be redetermined.

If the data value (k) in the dynamic incremental register 150 at step172 has been incremented indicating no change in the error correctionalgorithm, the FEC dynamic remote station processor 212 determineswhether the number of downlink time frames 108(1) in the next downlinkmulti-frame 156(1) should be increased or maintained. The CPU 134determines the number of consecutive times the same error correctionalgorithm has been selected by accessing the dynamic incrementalregister 150 to obtain the current data value (k). The CPU 134 alsodetermines the high stability threshold value by accessing the highstability threshold set register 154 to obtain the data value (Q). TheCPU 134 compares the data value (k) to the data value (Q). If the datavalue (k) is equal to or greater than the data value (Q), the CPU 134increments the data value (L) in the multi-frame register 142 by aparticular number, increasing the number of time frames 108 in the nextmulti-frame 156. The CPU 134 resets the data value (k) to “0”, so thatthe stability of the communication channel quality can be redetermined.If the data value (k) is less than the data value (Q), the CPU 134 doesnot change the data value (L), maintaining the number of downlink timeframes 108(1) in the next downlink multi-frame 156(1) to its currentvalue. The CPU 134 does not reset the data value (k), so that thecurrent number of consecutive times the same error correction algorithmhas been selected is taken into account during the next determination ofthe stability of the communication channel quality.

At step 176, the FEC dynamic remote station 106 transmits uplink controldata to the FEC dynamic central station 104 during the next availablecontrol time slot. The uplink control data indicates the errorcorrection algorithm selected by the FEC dynamic remote station 106, thenext downlink time frame 108(1) during which the FEC dynamic remotestation 106 selects an error correction algorithm, and if applicable, anARQ signal indicating the receipt of a defective corrected downlinkbearer data packet as described above.

The FEC dynamic central station 104 receives the uplink errorcorrectable bearer data packet from the FEC dynamic remote station 106and processes the uplink control data. The FEC dynamic central station104 transmits downlink control data to the FEC dynamic remote station106 during the next available downlink control time slot. The downlinkcontrol data indicates whether the error correction algorithm selectionis approved or denied. If the FEC dynamic central station processor 112′determines that the selected error correction algorithm should beemployed, the downlink control data indicates approval of the selectederror correction algorithm. On the other hand, if the FEC dynamiccentral station processor 112′ determines that the selected errorcorrection algorithm should not be employed, such as, if the selectederror correction algorithm is not compatible with the wirelesscommunication system 100 or the available overhead or central stationdoes not support the error correction algorithm, the downlink controldata indicates denial of the selected error correction algorithm.

The FEC dynamic remote station 106 receives the downlink control data,and accordingly either resets the data value (B) of the downlinkalgorithm specification register 138 to the selected data value (B) ifthe selected error correction algorithm was approved by the FEC dynamiccentral station processor 212′, or does not reset the data value (B) ofthe downlink algorithm specification register 138 to the selected datavalue (B), if the selected error correction algorithm was denied by theFEC dynamic central station processor 212′.

The FEC dynamic central station processor 112′, in turn, resets the datavalue (A′) in the downlink algorithm specification register 136′ equalto the data value (B).

Rather than synchronizing the error correction algorithm used by thecentral station 104 and remote station 106 to respectively encode andprocess a downlink bearer data packet by sending a confirmation ordenial signal during a dedicated control time slot as described abovewith respect to step 176, synchronization of the error correctionalgorithm can be accomplished by encoding each downlink bearer datapacket with a highly protected code word indicating the error correctionalgorithm that was employed to encode the particular downlink bearerdata packet with error correction data. During processing of thedownlink bearer data packet, the remote station 106 can decode the codeword to determine the error correction algorithm to be employed toprocess the downlink bearer data packet. More alternatively, the remotestation 106 can process the downlink bearer data packet with allavailable error correction algorithms, and use the best corrected bearerdata packet.

After synchronization of the error correction algorithm, the wirelesscommunications system 100 then returns to steps 160 and 162 where theerror correction encoder 118′ of the FEC dynamic central station 104 andthe error correction decoder 118 of the FEC dynamic remote station 106are configured to employ the particular error correction algorithm asspecified by the data value (A′) and data value (B).

If an error correction algorithm was selected at step 172, and thus, thedata value (i) in the time frame incremental register 140 was reset to“0”, the next downlink error correctable bearer data packet transmittedby the FEC dynamic central station 104 and received by the FEC dynamicremote station 106 will occur during the first time frame 108 of thenext multi-frame 156. Contrariwise, if an error correction algorithm wasnot selected at step 172, and thus, the data value (i) in the time frameincremental register 140 was not reset to “0”, the next downlink errorcorrectable bearer data packet transmitted by the FEC dynamic centralstation 104 and received by the FEC dynamic remote station 106 willoccur during the next downlink time frame 108(1) of the current downlinkmulti-frame 156(1).

The steps performed by the FEC dynamic central station processor 112′and the FEC dynamic remote station processor 112, in effecting theuplink transmission of consecutive error correctable bearer data packetsaccording to the dynamic FEC arrangement of the present invention, arereciprocal to and independent of those described above, with respect tothe downlink transmission of consecutive error correctable bearer datapackets. For purposes of simplicity and terseness, these steps will notbe described.

If the current BER level, rather than the current BLER is obtained,steps 258, 266, 268 and 272 (FIG. 9) are performed in place of steps158, 166, 168 and 172. Step 258 is similar to step 158 with theexception that, rather than initializing the minimum-level BLERthreshold set register 146 and the maximum-level BLER threshold setregister 148, the data value (R) in the first-level BER threshold setregister 246 and the data value (S) in the second level BLER thresholdset register 248 are initialized to respectively set the first-level BERthreshold level and the second-level BER threshold level.

Step 266 is similar to step 166 with the exception that the errorcorrection decoder 130, rather than the error detection decoder 132, isemployed to measure the current BER level rather than the current BLERlevel. That is, prior to correcting a downlink bearer data packet, theerror correction decoder 130 measures the bit errors in the downlinkbearer data packet and sends a corresponding control signal to theprocessor indicating the existence and number of bit errors in thedownlink bearer data packet.

Step 268 is similar to step 168 with the exception that the total numberof errors in each uncorrected downlink bearer data packet are tracked(i.e., the current BER is measured), rather than the existence of adefective corrected downlink bearer data packet (i.e., the current BLERis measured). That is, if the error correction decoder 130 receives adownlink bearer data packet with no bit errors, the error correctiondecoder 130 sends a control signal to the processor 112 indicating thatthe error correction decoder 130 possesses a downlink bearer data packetwith no bit errors. If the error correction decoder 130 receives adownlink bearer data packet with at least one error, the errorcorrection decoder 130 sends a control signal to the processor 112indicating the existence and number of bit errors in the downlink bearerdata packet. The CPU 234 increments the data value (p) in the BERincremental register 244 by the number of bit errors detected. Thedownlink bearer data packet is then corrected and processed as describedabove.

Step 272 is similar to step 172, with the exception that absoluteselection, rather than relative selection, of the error correctionalgorithm is performed. If the current BER level falls within the rangebelow the first-level threshold, no error correction algorithm isselected. If the current BER level falls within the range between thefirst-level threshold and the second-level threshold, the low-levelerror correction algorithm is selected. If the current BER level fallswithin the range above the second-level threshold, the high-level errorcorrection algorithm is selected.

Thus, the CPU 234 determines a current BER level by accessing the BERincremental register 244 to obtain the current data value (p), anddetermines a first-level BER threshold level by accessing thefirst-level BER threshold set register 246 to obtain the current datavalue (R) and a second-level BER threshold level by accessing thesecond-level BER threshold set register 248 to obtain the current datavalue (S). The CPU 234 compares the data value (p) to the data values(R) and (S). If the data value (p) is less than the data value (R), theCPU 234 selects the data value (B) as “0”, indicating that the no errorcorrection algorithm should be selected. If the data value (p) is equalto or greater than the data value (S), the CPU 234 selects the datavalue (B) as “2”, indicating that the high-level error correctionalgorithm should be selected. In all other cases, the CPU 234 selectsthe data value (B) as “1”, indicating that the low-level errorcorrection algorithm should be selected. If data value (B) has changed,the CPU 234 does not increment the data value (k). If data value (B) hasnot changed, the CPU 234 increments by one the data value (k).

Subsequent to the proposed selection of the error correction algorithm,the CPU 234 resets the data value (i) in the time frame incrementalregister 140 to “0” and the data value (p) in the BER incrementalregister 244 to “0”, so that they are initialized for the nextmulti-frame 156.

Operation of the wireless communications system 100 in the TDMA/TDDformat is similar to that described above with respect to the TDMA/FDDformat, with the exception that the reciprocal error correctable bearerdata packet transmissions between the FEC dynamic central station 104and the FEC dynamic remote station 106 occur during the samedownlink/uplink time frame 108(3), i.e., same frequency.

The present inventions are not limited to the wireless communicationsystem disclosed above and may include other types of wirelesscommunications systems, such as, e.g., satellite based communicationssystems, or other types of wire-based systems, such as, e.g., LANsystems or fiber optic networks.

The present inventions can be used in an out-of-band FEC system, whereinerror correction data is transmitted and received in out-of-band timeslots, as described in further detail in copending application Ser. No.09/314,580 filed concurrently herewith, which is fully and expresslyincorporated herein by reference.

Thus, an improved apparatus and method for improving the data throughputof a communications system is disclosed. While embodiments andapplications of this invention have been shown and described, it wouldbe apparent to those skilled in the art that many more modifications arepossible without departing from the inventive concepts herein.

The invention, therefore is not to be restricted except in the spirit ofthe appended claims.

1. A method of selecting an error correction algorithm in acommunications system, the method comprising: dividing each time frameof a multi-frame into a plurality of time slots; determining an errorrate level of a communication channel based on a plurality of bearerdata packets when received during said multi-frame; selecting an errorcorrection algorithm from a plurality of error correction algorithmstaking into account said error rate level; determining the dynamicquality of said communication channel; and adjusting the number of timeframes in a multi-frame based on said dynamic quality.
 2. The method ofclaim 1, wherein said plurality of bearer data packets comprises trafficdata.
 3. The method of claim 2, wherein said selected error correctionalgorithm has an overhead level, and wherein the amount of said trafficdata is inversely varied with said overhead.
 4. The method of claim 1,and wherein said error rate level determination comprises correctingsaid plurality of bearer data packets and detecting a number ofdefective bearer data packets to obtain a current block error rate(BLER) level, and wherein said error correction algorithm determinationis based on said current BLER level.
 5. The method of claim 4, whereinsaid error correction algorithm selection comprises setting a minimumBLER threshold level and a maximum BLER threshold level to create anacceptable BLER range, selecting a current error correction algorithm ifsaid acceptable BLER range includes said current BLER level andselecting an error correction algorithm different from said currenterror correction algorithm if said acceptable BLER range does notinclude said current BLER level.
 6. The method of claim 5, wherein saidplurality of error correction algorithm comprise algorithms comprisesdiffering overhead levels, and said error correction algorithmdetermination further comprises selecting an error correction algorithmwith a next lower overhead than that of said current error correctionalgorithm if said current BLER level is below said minimum BLERthreshold level and selecting an error correction algorithm with a nexthigher overhead than that of said current error correction algorithm ifsaid current BLER level is above said maximum BLER threshold level. 7.The method of claim 1, wherein said error rate level determinationcomprises detecting a number of bit errors in said plurality of bearerdata packets to obtain a bit error rate (BER) level, and wherein saiderror rate level determination is based on said current BER level. 8.The method of claim 7, wherein said error correction algorithm selectioncomprises setting at least one BER threshold level to create a pluralityof BER ranges corresponding to the plurality of error correctionalgorithmns algorithms, and selecting an error correction algorithm thatcorresponds to the BER range that includes the current BER level.
 9. Themethod of claim 1, wherein each bearer data packet of said plurality ofbearer data packets is respectively received during a time slot of saideach time frame of said multi-frame, and wherein said error correctionalgorithm selection comprises selecting said error correction algorithmduring the last time frame of said multi-frame.
 10. The method of claim1, wherein said plurality of error correction algorithms includes analgorithm which, when used, does not by itself correct any errors. 11.The method of claim 1, wherein said plurality of error correctionalgorithms includes an algorithm which, when used, does not by itselfcorrect any errors, a low-level error correction algorithm and ahigh-level error correction algorithm.
 12. The method of claim 1,wherein said plurality of bearer data packets are wirelessly transmittedbetween a central station and a remote station.
 13. An article,comprising: a non-transitory processor accessible medium having storedthereon instructions that, when executed by a processor, result inselecting an error correction algorithm in a communications system by:dividing each time frame of a multi-frame into a plurality of timeslots; determining an error rate level of a communication channel basedon a plurality of bearer data packets when received during saidmulti-frame; selecting an error correction algorithm from a plurality oferror correction algorithms taking into account said error rate level;determining the dynamic quality of said communication channel; andadjusting the number of time frames in a multi-frame based on saiddynamic quality.
 14. The article of claim 13, wherein each bearer datapacket of said plurality of bearer data packets is respectively receivedduring a time slot of said each time frame of said multi-frame, andwherein said error correction algorithm selection comprises selectingsaid error correction algorithm during the last time frame of saidmulti-frame.
 15. The article of claim 13, wherein said plurality oferror correction algorithms includes an algorithm which, when used, doesnot by itself correct any errors.
 16. The article of claim 13, whereinsaid plurality of error correction algorithms includes an algorithmwhich, when used, does not correct any errors, a low-level errorcorrection algorithm and a high-level error correction algorithm. 17.The article of claim 13, wherein said plurality of bearer data packetsare wirelessly transmitted between a central station and a remotestation.
 18. The article of claim 13, wherein said plurality of bearerdata packets comprises traffic data.
 19. The article of claim 18,wherein said selected error correction algorithm has an overhead level,and wherein the amount of said traffic data is inversely varied withsaid overhead.
 20. The article of claim 13, wherein said error ratelevel determination comprises detecting a number of bit errors in saidplurality of bearer data packets to obtain a bit error rate (BER) level,and wherein said error rate level determination is based on said currentBER level.
 21. The article of claim 20, wherein said error correctionalgorithm selection comprises setting at least one BER threshold levelto create a plurality of BER ranges corresponding to the plurality oferror correction algorithms, and selecting an error correction algorithmthat corresponds the BER range that includes the current BER level. 22.The article of claim 13, wherein said error rate level determinationcomprises correcting said plurality of bearer data packets and detectinga number of defective bearer data packets to obtain a current blockerror rate (BLER) level, and wherein said error correction algorithmdetermination is based on said current BLER level.
 23. The article ofclaim 22, wherein said error correction algorithm selection comprisessetting a minimum BLER threshold level and a maximum BLER thresholdlevel to create an acceptable BLER range, selecting a current errorcorrection algorithm if said acceptable BLER range includes said currentBLER level and selecting an error correction algorithm different fromsaid current error correction algorithm if said acceptable BLER rangedoes not include said current BLER level.
 24. The article of claim 23,wherein said plurality of error correction algorithms comprisesdiffering overhead levels, and said error correction algorithmdetermination further comprises selecting an error correction algorithmwith a next lower overhead than that of said current error correctionalgorithm if said current BLER level is below said minimum BLERthreshold level and selecting an error correction algorithm with a nexthigher overhead than that of said current error correction algorithm ifsaid current BLER level is above said maximum BLER threshold level. 25.An apparatus, comprising: a receiver to receive bearer data packets; anda processor to determine an error rate level of a communication channelbased on a plurality of bearer data packets when received by saidreceiver during a multi-frame divided into a plurality of time slots,wherein said processor selects an error correction algorithm from aplurality of error correction algorithms taking into account said errorrate level, determines the dynamic quality of said communicationchannel, and adjusts the number of time frames in a multi-frame based onsaid dynamic quality.
 26. The apparatus of claim 25, wherein each bearerdata packet of said plurality of bearer data packets is respectivelyreceived during a time slot of said each time frame of said multi-frame,and wherein said error correction algorithm selection comprisesselecting said error correction algorithm during the last time frame ofsaid multi-frame.
 27. The apparatus of claim 25, wherein said pluralityof error correction algorithms includes an algorithm which, when used,does not by itself correct any errors.
 28. The apparatus of claim 25,wherein said plurality of error correction algorithms includes analgorithm which, when used, does not by itself correct any errors, alow-level error correction algorithm and a high-level error correctionalgorithm.
 29. The apparatus of claim 25, wherein said plurality ofbearer data packets are wirelessly transmitted between a central stationand a remote station.
 30. The apparatus of claim 25, wherein saidplurality of bearer data packets comprises traffic data.
 31. Theapparatus of claim 30, wherein said selected error correction algorithmhas an overhead level, and wherein the amount of said traffic data isinversely varied with said overhead.
 32. The apparatus of claim 25,wherein said error rate level determination comprises detecting a numberof bit errors in said plurality of bearer data packets to obtain a biterror rate (BER) level, and wherein said error rate level determinationis based on said current BER level.
 33. The apparatus of claim 32,wherein said error correction algorithm selection comprises setting atleast one BER threshold level to create a plurality of BER rangescorresponding to the plurality of error correction algorithms, andselecting an error correction algorithm that corresponds to the BERrange that includes the current BER level.
 34. The apparatus of claim25, wherein said error rate level determination comprises correctingsaid plurality of bearer data packets and detecting a number ofdefective bearer data packets to obtain a current block error rate(BLER) level, and wherein said error correction algorithm determinationis based on said current BLER level.
 35. The apparatus of claim 34,wherein said error correction algorithm selection comprises setting aminimum BLER threshold level and a maximum BLER threshold level tocreate an acceptable BLER range, selecting a current error correctionalgorithm if said acceptable BLER range includes said current BLER leveland selecting an error correction algorithm different from said currenterror correction algorithm if said acceptable BLER range does notinclude said current BLER level.
 36. The apparatus of claim 35, whereinsaid plurality of error correction algorithms comprises differingoverhead levels, and said error correction algorithm determinationfurther comprises selecting an error correction algorithm with a nextlower overhead than that of said current error correction algorithm ifsaid current BLER level is below said minimum BLER threshold level andselecting an error correction algorithm with a next higher overhead thanthat of said current error correction algorithm if said current BLERlevel is above said maximum BLER threshold level.